module myADC( clk,D,neg_q,q_imag,i_real );

	input  clk;
	input  D;
	output  neg_q;
	output  q_imag;
	output  i_real;

	parameter DATA_WIDTH=18;
	parameter ORDER=74;//TAPS=75
//////////////////////////////////////
	wire clkop;
	wire lock;

	reg  [ORDER:0]z=0;
	reg  signed [DATA_WIDTH-1:0] coef[ORDER:0];
	reg  signed [DATA_WIDTH+2:0] sum=0;
	reg  [DATA_WIDTH+2:0] sum2=0;
	wire  [DATA_WIDTH-1:0] sum_unsigned;
//////////////////////////////////////
	reg outclocken=1;
	reg reset=1;  
//////////////////////////////////////
	//use myPLL instance
	myPLL myPLL(.CLK(clk),.CLKOP(clkop),.LOCK(lock));

	always @(posedge clk)begin
		if(reset)begin 
coef[0]<=-341;
coef[1]<=-298;
coef[2]<=-129;
coef[3]<=201;
coef[4]<=463;
coef[5]<=443;
coef[6]<=159;
coef[7]<=-128;
coef[8]<=-154;
coef[9]<=59;
coef[10]<=163;
coef[11]<=-180;
coef[12]<=-870;
coef[13]<=-1304;
coef[14]<=-840;
coef[15]<=538;
coef[16]<=1995;
coef[17]<=2408;
coef[18]<=1326;
coef[19]<=-518;
coef[20]<=1743;
coef[21]<=-1536;
coef[22]<=-464;
coef[23]<=-4;
coef[24]<=-1027;
coef[25]<=-2623;
coef[26]<=-2553;
coef[27]<=703;
coef[28]<=5963;
coef[29]<=9421;
coef[30]<=7264;
coef[31]<=-930;
coef[32]<=-10874;
coef[33]<=-15890;
coef[34]<=-11602;
coef[35]<=435;
coef[36]<=13167;
coef[37]<=18573;
coef[38]<=13167;
coef[39]<=435;
coef[40]<=-1160;
coef[41]<=-15890;
coef[42]<=-10874;
coef[43]<=-930;
coef[44]<=7264;
coef[45]<=9421;
coef[46]<=5963;
coef[47]<=703;
coef[48]<=-2553;
coef[49]<=-2623;
coef[50]<=-1027;
coef[51]<=-4;
coef[52]<=-464;
coef[53]<=-1536;
coef[54]<=-1743;
coef[55]<=-518;
coef[56]<=1326;
coef[57]<=2408;
coef[58]<=1995;
coef[59]<=538;
coef[60]<=-840;
coef[61]<=-1304;
coef[62]<=-870;
coef[63]<=-180;
coef[64]<=163;
coef[65]<=59;
coef[66]<=-154;
coef[67]<=-128;
coef[68]<=159;
coef[69]<=443;
coef[70]<=463;
coef[71]<=201;
coef[72]<=-129;
coef[73]<=-298;
coef[74]<=-341;

					
			reset=0;
		end else begin	
		end

	end

	always @(posedge clkop )begin
		z= z<<1; //1bit shift left   blocking mode used
		z[0]=D;  //z[0]<=input data
		if(!reset)begin	
			 // z[0] is '0' or '1','multiply'replaced with 'add'	
			sum=0;		
			sum= (z[0]?coef[0]:0)+(z[1]?coef[1]:0)+(z[2]?coef[2]:0)+(z[3]?coef[3]:0)+(z[4]?coef[4]:0)+(z[5]?coef[5]:0)
				+(z[6]?coef[6]:0)+(z[7]?coef[7]:0)+(z[8]?coef[8]:0)+(z[9]?coef[9]:0)+(z[10]?coef[10]:0)
				+(z[11]?coef[11]:0)+(z[12]?coef[12]:0)+(z[13]?coef[13]:0)+(z[14]?coef[14]:0)+(z[15]?coef[15]:0)
				+(z[16]?coef[16]:0)+(z[17]?coef[17]:0)+(z[18]?coef[18]:0)+(z[19]?coef[19]:0)+(z[20]?coef[20]:0)
				+(z[21]?coef[21]:0)+(z[22]?coef[22]:0)+(z[23]?coef[23]:0)+(z[24]?coef[24]:0)+(z[25]?coef[25]:0)
				+(z[26]?coef[26]:0)+(z[27]?coef[27]:0)+(z[28]?coef[28]:0)+(z[29]?coef[29]:0)+(z[30]?coef[30]:0)

+(z[31]?coef[31]:0)
+(z[32]?coef[32]:0)+(z[33]?coef[33]:0)+(z[34]?coef[34]:0)+(z[35]?coef[35]:0)+(z[36]?coef[36]:0)
+(z[37]?coef[37]:0)+(z[38]?coef[38]:0)+(z[39]?coef[39]:0)+(z[40]?coef[40]:0)+(z[41]?coef[41]:0)
+(z[42]?coef[42]:0)+(z[43]?coef[43]:0)+(z[44]?coef[44]:0)+(z[45]?coef[45]:0)+(z[46]?coef[46]:0)
+(z[47]?coef[47]:0)+(z[48]?coef[48]:0)+(z[49]?coef[49]:0)+(z[50]?coef[50]:0)+(z[51]?coef[51]:0)
+(z[52]?coef[52]:0)+(z[53]?coef[53]:0)+(z[54]?coef[54]:0)+(z[55]?coef[55]:0)+(z[56]?coef[56]:0)
+(z[57]?coef[57]:0)+(z[58]?coef[58]:0)+(z[59]?coef[59]:0)+(z[60]?coef[60]:0)+(z[61]?coef[61]:0)
+(z[62]?coef[62]:0)+(z[63]?coef[63]:0)+(z[64]?coef[64]:0)+(z[65]?coef[65]:0)+(z[66]?coef[66]:0)
+(z[67]?coef[67]:0)+(z[68]?coef[68]:0)+(z[69]?coef[69]:0)+(z[70]?coef[70]:0)+(z[71]?coef[71]:0)
+(z[72]?coef[72]:0)+(z[73]?coef[73]:0)+(z[74]?coef[74]:0);
			
			// This method does not work.why?
		/*	for(i=0;i<ORDER;i=i+1)begin  
				sum=sum+ z[i] ? coef[i]:0;			
			end*/
			//sum_unsigned=(sum+16'h7fff);	
			sum2=sum+21'hfffff;	//to unsigned
		end else begin
		end
	end

assign neg_q=~z[0];
assign sum_unsigned=sum2[19:2];//18bit is sufficient for 50dBC

//accum	#(16)	accum_real(clk,sum_unsigned,i_real);
//accum	#(16)	accum_real2(clk,sum_unsigned,q_imag);
accum	#(DATA_WIDTH)	accum_real(clk,sum_unsigned,i_real);
accum	#(DATA_WIDTH)	accum_real2(clk,sum_unsigned,q_imag);
endmodule

module accum(clk,VDA,cy_out);

	parameter DATA_WIDTH=16;

	input 	clk;
	input [DATA_WIDTH-1:0]	VDA;
	output cy_out;


///// internal variables ////////
	reg	[DATA_WIDTH-1:0]	R=0;
	reg	cy=0;

	assign cy_out= cy;

	always @(posedge clk) begin
		{cy,R} <=R+ VDA;
	end

endmodule