module myADC128( clk,D,neg_q,q );

	parameter DATA_WIDTH=18;
	parameter DECIM=32;
	parameter TAPS=128;
	input  clk;
	input  D;
	output  neg_q;
	output  q;
//////////// PLL //////////////////////////
	wire mixed_sig_1bit;
	wire clkop;
	wire lock;
	reg Qinner=0;
/////////// sin wave ///////////////////////////
	reg	[9:0]theta=0;
	wire	signed[DATA_WIDTH-1:0]sin_signed;
	reg	signed[DATA_WIDTH-1:0]mixed_signed=0;
	reg 	[DATA_WIDTH-1:0]mixed_unsigned=0;
/////////// delay etc///////////////////////////
	reg decim_clock=0;
	reg [7:0]count=0;

	reg [TAPS-1:0]z;

	reg [7:0]decim_count=0;	
	reg reset=1;
	reg  signed [DATA_WIDTH-1:0] coef[TAPS-1:0];
	reg  [DATA_WIDTH+1:0] sum=0;
	reg [DATA_WIDTH-1:0] sum_unsigned=0;
	wire [DATA_WIDTH-1:0] result;

	integer i;
////////////////////////////////////////////////////////////////////////////////////////
	//use myPLL instance & generate sin wave
	myPLL myPLL(.CLK(clk),.CLKOP(clkop),.LOCK(lock));
	sin     sin(.Clock(clk), .ClkEn(1), .Reset(0), .Theta(theta), .Sine(sin_signed));
//need for 1bit bandpass delta sigma ADC
	assign neg_q=~Qinner;
//multiplier: sampled input D * sin wave

	accum	#(DATA_WIDTH)  accum3(clkop,mixed_unsigned,mixed_sig_1bit);


	assign result=sum_unsigned;
	accum	#(DATA_WIDTH)  accum4(clkop,result,q);

	always@(posedge clkop) begin
		if(reset==0) begin
/////////// need for 1bit bandpass ADC///////
			Qinner =D;
	 		mixed_signed= (Qinner ? sin_signed:-sin_signed);
			mixed_unsigned=mixed_signed+18'h1ffff;
/////////// delay ///////////////////////////

			z=z<<1;

			z[0]=mixed_sig_1bit;

			sum=0;

			for(i=TAPS-1;i>=0;i=i-1) begin
				sum=sum+(z[i]?coef[i]:0);
			end

//			decim_count=decim_count+1;

//			if(decim_count==DECIM) begin	//decimatiton:1/DECIM

				sum_unsigned=sum[DATA_WIDTH-1:0];
//				decim_count=0;   
			
//			end 
		end
	
	end


	initial begin	//for simulation only
		
		z[0]<=0;
		
	end

	always@(posedge clk) begin

	if(reset)begin 

/*		for(i=0;i<TAPS;i=i+1) begin
			coef[i]=i;
		end*/
coef[0]<=	300	;
coef[1]<=	91	;
coef[2]<=	105	;
coef[3]<=	120	;
coef[4]<=	136	;
coef[5]<=	153	;
coef[6]<=	171	;
coef[7]<=	190	;
coef[8]<=	211	;
coef[9]<=	233	;
coef[10]<=	256	;
coef[11]<=	280	;
coef[12]<=	306	;
coef[13]<=	332	;
coef[14]<=	360	;
coef[15]<=	390	;
coef[16]<=	420	;
coef[17]<=	451	;
coef[18]<=	484	;
coef[19]<=	518	;
coef[20]<=	553	;
coef[21]<=	589	;
coef[22]<=	625	;
coef[23]<=	663	;
coef[24]<=	701	;
coef[25]<=	741	;
coef[26]<=	781	;
coef[27]<=	821	;
coef[28]<=	863	;
coef[29]<=	904	;
coef[30]<=	946	;
coef[31]<=	989	;
coef[32]<=	1031	;
coef[33]<=	1074	;
coef[34]<=	1117	;
coef[35]<=	1159	;
coef[36]<=	1202	;
coef[37]<=	1244	;
coef[38]<=	1286	;
coef[39]<=	1327	;
coef[40]<=	1367	;
coef[41]<=	1407	;
coef[42]<=	1446	;
coef[43]<=	1485	;
coef[44]<=	1522	;
coef[45]<=	1558	;
coef[46]<=	1592	;
coef[47]<=	1626	;
coef[48]<=	1658	;
coef[49]<=	1688	;
coef[50]<=	1717	;
coef[51]<=	1744	;
coef[52]<=	1770	;
coef[53]<=	1793	;
coef[54]<=	1815	;
coef[55]<=	1835	;
coef[56]<=	1852	;
coef[57]<=	1868	;
coef[58]<=	1881	;
coef[59]<=	1893	;
coef[60]<=	1902	;
coef[61]<=	1908	;
coef[62]<=	1913	;
coef[63]<=	1915	;
coef[64]<=	1915	;
coef[65]<=	1913	;
coef[66]<=	1908	;
coef[67]<=	1902	;
coef[68]<=	1893	;
coef[69]<=	1881	;
coef[70]<=	1868	;
coef[71]<=	1852	;
coef[72]<=	1835	;
coef[73]<=	1815	;
coef[74]<=	1793	;
coef[75]<=	1770	;
coef[76]<=	1744	;
coef[77]<=	1717	;
coef[78]<=	1688	;
coef[79]<=	1658	;
coef[80]<=	1626	;
coef[81]<=	1592	;
coef[82]<=	1558	;
coef[83]<=	1522	;
coef[84]<=	1485	;
coef[85]<=	1446	;
coef[86]<=	1407	;
coef[87]<=	1367	;
coef[88]<=	1327	;
coef[89]<=	1286	;
coef[90]<=	1244	;
coef[91]<=	1202	;
coef[92]<=	1159	;
coef[93]<=	1117	;
coef[94]<=	1074	;
coef[95]<=	1031	;
coef[96]<=	989	;
coef[97]<=	946	;
coef[98]<=	904	;
coef[99]<=	863	;
coef[100]<=	821	;
coef[101]<=	781	;
coef[102]<=	741	;
coef[103]<=	701	;
coef[104]<=	663	;
coef[105]<=	625	;
coef[106]<=	589	;
coef[107]<=	553	;
coef[108]<=	518	;
coef[109]<=	484	;
coef[110]<=	451	;
coef[111]<=	420	;
coef[112]<=	390	;
coef[113]<=	360	;
coef[114]<=	332	;
coef[115]<=	306	;
coef[116]<=	280	;
coef[117]<=	256	;
coef[118]<=	233	;
coef[119]<=	211	;
coef[120]<=	190	;
coef[121]<=	171	;
coef[122]<=	153	;
coef[123]<=	136	;
coef[124]<=	120	;
coef[125]<=	105	;
coef[126]<=	91	;
coef[127]<=	300	;



		reset=0;
		end else begin
			theta=theta+64;//7.1MHz@113.6MHz. sin wave
			// counter for decimation
			count=count+1;
			if(count==DECIM)begin
				decim_clock=~decim_clock;
				count=0;
			end else begin
			end
		end
	end


endmodule

module accum(clk,VDA,cy_out);

	parameter DATA_WIDTH2=18;
	input 	clk;
	input [DATA_WIDTH2-1:0]	VDA;
	output cy_out;

///// internal variables ////////
	reg	[DATA_WIDTH2-1:0]	R=0;
	reg	cy=0;

	assign cy_out= cy;

	always @(posedge clk) begin
		{cy,R} <=R+ VDA;
	end

endmodule