module Yn(clk,u_out );

	input clk;
	output signed[9:0]u_out;//dummy
	parameter DECIM=64;     //Fix to 1/64 decimation 
	parameter BITS=31;      //accumulator & delay components bits

	reg signed [2*BITS-16:0]decimated_out=0;
	reg signed [2*BITS-16:0]decimated_out2=0;
	reg signed [2*BITS-16:0]decimated_out3=0;
	reg signed [2*BITS-19:0]decimated_out4=0;
// differntial part: delay //////////////
	reg signed[2*BITS-16:0]z_decimated[1:0];
	reg signed[2*BITS-16:0]z2_decimated[1:0]; 
	reg signed[2*BITS-16:0]z3_decimated[1:0]; 
	reg signed[2*BITS-19:0]z4_decimated[1:0]; 
// 1st integrator /////////
	reg signed[BITS+4:0]yn=0;
	reg signed[BITS+4:0]yn_1=0;
// 1st integrator: delay 
	reg signed[15:0]z[1:0];//same as sine wave bits

// 2nd integrator /////////
	reg signed[2*BITS-16:0]un=0;
	reg signed[2*BITS-16:0]un_1=0;	
// 2nd integrator: delay 
	reg signed[2*BITS-16:0]z2[1:0];

// 3rd integrator /////////
	reg signed[2*BITS-16:0]vn=0;
	reg signed[2*BITS-16:0]vn_1=0;	
// 3rd integrator: delay 
	reg signed[2*BITS-16:0]z3[1:0];

// 4th integrator /////////
	reg signed[2*BITS-16:0]wn=0;
	reg signed[2*BITS-16:0]wn_1=0;	
// 4th integrator: delay 
	reg signed[2*BITS-16:0]z4[1:0];
// for sin wave ///////////	
	reg [9:0]theta=0;
	wire signed[15:0]sine;
// for decimation /////////////
	reg [7:0]count=0;
	reg decim_clk=0;
	wire clk2;
//////////////////////////////////////
sin sin(.Clock(clk2), .ClkEn(1), .Reset(0), .Theta(theta), .Sine(sine));
	
	always@(posedge decim_clk)begin
		//1st differential
		z_decimated[1]=z_decimated[0];
		z_decimated[0]=wn;
		decimated_out=z_decimated[0]-z_decimated[1];
		//2nd differential 
		z2_decimated[1]=z2_decimated[0];
		z2_decimated[0]=decimated_out;
		decimated_out2=z2_decimated[0]-z2_decimated[1];

		//3rd differential 
		z3_decimated[1]=z3_decimated[0];
		z3_decimated[0]=decimated_out2;
		decimated_out3=z3_decimated[0]-z3_decimated[1];

		//4th differential 
		z4_decimated[1]=z4_decimated[0];
		z4_decimated[0]=decimated_out3;
		decimated_out4=z4_decimated[0]-z4_decimated[1];
	end

	always@(posedge clk)begin 
		count=count+1;
		if(count==DECIM)begin
			count=0;
			decim_clk=~decim_clk;
		end
		else begin
		end

		z[1]=z[0];z[0]=sine;
		z2[1]=z2[0];z3[1]=z3[0];
		z4[1]=z4[0];

		//1st integral:yn
		yn=yn_1+z[0];
		yn_1=yn;
		z2[0]=yn;
		//2nd integral:un
		un=un_1+z2[0];
		un_1=un;
		z3[0]=un;
		//3rd integral:vn
		vn=vn_1+z3[0];
		vn_1=vn;
		z4[0]=vn;
		//4th integral:wn
		wn=wn_1+z4[0];
		wn_1=wn;
	end
	always@(posedge clk2)begin
		theta=theta+1; //to create sin wave
	end		

	initial begin
		z[0]<=0; z[1]<=0;
	end

endmodule